Until the advent of deep sub micron integrated circuit processes, timing behavior of integrated circuits has been dictated by transistor considerations, mostly transistor travel time and the number of logic levels a signal traverses during a clock cycle. Accurate models of transistor device parameters were the key element for the prediction of circuit timing behavior.
For feature sizes larger than 0.35 μm wire delay is typically less than 20% of total timing delay. To account for the 20% contribution to total timing delay high precision delay estimates were not required for wire delay. A relatively large (e.g., 25%) uncertainty in extracting resistance and/or capacitance values results in approximately a 4% overall error in time delay modeling.
Computer aided design (CAD) programs used for integrated circuit design used simplified models to compute wire delay from resistance and capacitance data extracted using a layout database. Resistance and capacitance models that provide less than 25% uncertainty are well known in the art. For example, resistance estimates can be generated based on the geometric shape of the line to be estimated. Capacitance estimates can be generated based on a parallel plate capacitor model with perimeter fringe contribution corrections. These modeling approaches are useful for integrated circuit designs having device sizes greater than 0.35 μm.
However, as device sizes decrease the relative importance of wire delay increases. Wire extraction programs can be calibrated with accurate measurements of capacitance. One approach to accurate wire capacitance measurement is provided by B. W. McGaughy, J. C. Chen, D. Sylvester and C. Hu “A Simple Method for On-Chip Sub-Femto Farad Interconnect Capacitance Measurement,” IEEE Electron. Device Letters, Vol. 18, No. 1, pp. 21-23, Jan. 1997, (hereinafter referred to as “the IEEE paper”), which discloses a method for determining cross coupling capacitance. However, the method described in the IEEE paper suffers shortcomings that are explained in detail in a white paper by J. C. Chen and Roberto Suaya entitled “Proper On-Chip Capacitance Measurement,” (hereinafter referred to as “the white paper”). A brief overview of the white paper is provided below.
FIG. 1 represents the circuit 10 used in the IEEE paper to measure cross coupling capacitance. A general method to measure capacitance consists of measuring the total charge deposited on the capacitor, which can be accomplished by measuring DC currents, frequency of applied signals, and voltage. The following formula permits the determination of capacitance:I=CVddƒ  (Equation 1)where I is a DC current reading, C is a load capacitance, Vdd is the voltage supply level, and ƒ is the frequency of the waveforms applied.
The voltage waveform of FIG. 2 used in the IEEE paper are non-overlapping waveforms that provide, except for leakage, no current path between Vdd and ground in the circuit of FIG. 1. In the IEEE paper, the unknown capacitance is measured as the difference between two current readings on the two current meters 12, 14 in FIG. 1. The process is flawed because of charge redistribution. The capacitance coupling between two structures, depends on the presence of other nearby structures.
Consider in FIG. 1, two identical load structures, C and C′. The capacitance of C to ground on the right side of the structure is different from the capacitance C′ to ground on the left side. The difference is due to the redistribution of the electric field due to the presence of the second conductor 16. The capacitance difference can be quite large.
Configurations like the one shown in FIG. 3, where the load wire 18 and its neighbors 20, 22 are on the same physical layer and are separated by minimum distance, constitute a case where the direct application of the method of the IEEE paper would result in up to 70% error in the extraction of the unknown cross coupling capacitance. There is, in addition, the uncertainty related to the lack of equality in the capacitance of the transistors on the two sides of the mirror structure. This additional source of error becomes more significant as the device size decreases.